It is well known in the art to form split-gate memory cells as an array of such cells. For example, U.S. Pat. No. 7,868,375 discloses an array of memory cells, where each memory cell includes a floating gate, a control gate, a select gate, an erase gate, all formed on a substrate with a channel region defined between a source and drain regions. For efficient use of space, the memory cells are formed in pairs, with each pair sharing a common source region and erase gate.
It is also known to form both low voltage and high voltage logic devices on the same wafer die as the array of memory cells. Such logic devices can include transistors each having a source and drain, and a poly gate controlling the conductivity of the channel region between the source and drain. Conventional logic device formation includes forming the poly gate first (preferably forming the memory cell erase and select gates, and forming the logic device poly gates, using the same poly deposition processing), followed by an LDD implant to form the source and drain regions, whereby the source/drain regions are self-aligned to the poly gate. The poly gate blocks prevent any of the implant from reaching the channel region under the gate. High voltage logic devices are designed to operate at higher voltages, and are typically made by using a higher LDD implant energy so that the source/drain regions formed thereby have a higher breakdown voltage.
One problem is that as device geometries continue to scale down to smaller sizes, the poly gates for the logic devices are becoming too thin to effectively block the HV LDD implant, which can penetrate through the relatively thin poly gate and into the channel region (which adversely affects performance). The conventional solution is to lower the implant energy for the HV LDD implant to prevent such poly layer penetration. However, the lower implant energy results in a lower gated-diode breakdown voltage, thus undesirably limiting the operational voltage of high voltage transistors.